During the functioning of a processor, it may be necessary to interrupt the execution of a program for carrying out particular instructions. This is done by way of signals called interrupts. An interrupt controller receives these signals, and depending on the received interrupt, sends to the microprocessor an interrupt command and an interrupt vector that specifies the memory address where an interrupt service routine (ISR) to be run is stored.
The microprocessor stops the operation in progress, saves the state of the program that was executing so that it may be resumed later, and carries out the instructions of the respective ISR based upon the received interrupt. When the ISR finishes, the microprocessor restores the state of the program, and if there is not any other pending interrupt, resumes its execution from the point at which it had been interrupted.
Interrupt controllers commonly have priority registers that allow them to establish which interrupt among the many received and pending interrupts is to be processed first. A basic architecture of a known priority interrupt controller is depicted in FIG. 1. The interrupts INT0, . . . , INTm coming from peripherals are loaded in a pending interrupt register INT PENDING REG.
The circuit block IRQ MASK AND PRIORITY LOGIC comprises both the interrupts mask and a priority logic circuitry that receives an interrupt together with its priority level provided by the dedicated registers PRIORITY REGISTERS. The priority logic generates an interrupt request signal IRQ REQ and stores the relative priority HIGHEST PRIORITY INT in the register CURR IRQ PRIORITY REG.
The dashed perimeter delimits the circuit that processes the interrupt request signal and its priority HIGHEST PRIORITY INT. A state machine IRQ SM forms the core of the controller that receives the interrupt request signal and sends an interrupt command nIRQ to the processor. The interrupt request signal IRQ REQ selects an interrupt vector IRQ VECTOR corresponding to the required interrupt read from an interrupt table IRQ VECTOR REG containing interrupt vectors identifying ISR routines.
FIG. 1 shows registers CURR IRQ PRIORITY REG and PRIORITY STACK used for managing the nested interrupts. The register CURR IRQ PRIORITY REG stores the priority of the currently served interrupt. Should an interrupt with a higher priority be generated, the processing of the first interrupt is stopped and its priority is stored in the register PRIORITY STACK, and the new interrupt of the higher priority is processed and its priority is stored in the register CURR IRQ PRIORITY REG.
Once the processing of the interrupt is completed, the previously suspended interrupt is processed provided its priority has remained the highest of the priorities of all pending interrupts. When the processing of any interrupt is completed, its priority is canceled from the stack PRIORITY STACK by a command STACK PUSH/POP of the state machine IRQ SM.
An important parameter of interrupt controllers is the latency time of interrupts, that is, the time that elapses from the instant of reception of the interrupt in the register INT PENDING REG and the instant in which it is processed. It is always desirable that this time lag be as short as possible. Moreover, an interrupt must be processed within a certain maximum time (dead line) from the instant in which it is loaded in the pending interrupt register, otherwise the application managed by the running program may not function properly.
To prevent an interrupt from being processed after a pre-established dead line, the priority registers in known controllers are re-programmed at pre-established intervals. The duration of these intervals vary as a function of the register increasing the priority level of interrupts as a function of their latency in the pending interrupt register. In this way, interrupts with a longer latency are given a higher priority than the interrupts that have just been received, and are eventually processed before their latency reaches the dead line.
In contrast, the priorities of interrupts stored in the stack PRIORITY STACK are not incremented for preventing an interrupt previously suspended in favor of an incoming interrupt having a higher priority from suspending the processing of the incoming interrupt, and so on. Unfortunately, this technique of re-programming is not very convenient because the recurrent task of re-programming the priority registers burdens the microprocessor, thus slowing execution of the program.